FIG. 1 shows an integrated circuit of this kind. The logic blocks BL1, BL2 are, in practice, logic circuits or portions of logic circuits appropriately constituted by combinatorial logic components associated for the implementation of a particular logic function. In the example shown in FIG. 1, the configurable cells CC1, CC2 are D-latch type flip-flop circuits, including especially a functional D input and a Q output, respectively coupled to an output of a preceding logic block and to an input of a following logic block. The logic blocks BL1, BL2 and the configurable cells work together to form at least one functional circuit. A functional input of the first logic block BL1 forms an input of the integrated circuit to which a data input signal DIN is applied, and the output of the last latch circuit CC2 forms an output of the integrated circuit at which a data output signal DOUT is produced.
The increasing complexity of integrated circuits is being accompanied by a corresponding increase in the number of logic blocks, the complexity of the manufacturing methods and the variability of the performance of integrated circuits coming from a same silicon wafer or from a same batch of wafers.
The insertion of performance testing means into integrated circuits has therefore become a necessity to ensure the performance of the circuits and/or improve the performance of the manufacturing methods.
A testing technique, known as the <<scanpath>> method or <<internal scan method>>, in which the internal paths of an integrated circuit are tested, is used to test the functional blocks of the circuit for accurate functioning. This technique is worthwhile because it uses little surface area of silicon and it can therefore be implanted in finished products. However, this technique does not provide any indication on the performance of the functional blocks, i.e., on the real working speed of the blocks or on the current consumption of the functional blocks.
In another testing technique, test circuits are added on for the testing of the performance of the functional blocks. Test circuits of this kind are typically made out of systems of inverters and the precision of the measurement is at best equal to the delay introduced by an inverter. A test circuit must be used for each logic block to be tested. Furthermore, such test circuits are sensitive to variations in method from one circuit to another. The precision of the measurement and the possibilities of comparison between the circuits are thus limited. Finally, such test circuits are particularly costly in terms of silicon surface area so that, in practice, they are used only when making prototypes of integrated circuits but not in the definitive circuits.